1. Field of the Invention
The present invention generally relates to a method and system for generating test pulses, and more particularly to a method and system for programmable generating test pulses.
2. Description of the Prior Art
As is known, tests on electronic element such as IC (integrated circuit) could be categorized into the following three types, direct current parametric test, dynamic functional test, and alternating current test. Among these three types, dynamic functional test is more complicated and important than other tests. In order to perform dynamic functional test of an electronic element, it is required to have a driver for generating test pulses to drive the electronic element, a comparator for examining the output pulses of the electronic element, and a power supply for generating stable currency. Test pulses generated by the driver are sent into an electronic element to be tested. The electronic element to be tested is driven by these test pulses and produces correspondent output pulses, which would be received and examined by the comparator. At the end, the comparator would compare the received output pulses with a serial of predetermined pulses to determine the functional test result of the tested electronic element.
In this regard, test pulses are different for adapting to the different electronic element to be tested. It means that the driver for generating test pulses is also required to change for varied electronic elements. Since the test pulses for an electronic element are usually quite complicated and the differences of test pulses for different electronic elements are quite significant, the driver is needed to be customized for each electronic element. Therefore most of customized drivers are made of ASIC (Application Specified Integrated Circuit) that consumes lots of costs and time to design before test. Besides, the customized drivers are not reusable for other test cases.
Generally speaking, the input and output signals of an electronic element are called pulses, which have three measurable elements, time duration, voltage, and represented logical data, respectively. As shown in FIG. 1A, signal 10 is a serial of continuous pulses, which could be interpreted as a combination of a logical data 1 and a logical data 0. Logical data 1 and 0 may be represented by a correspondent higher voltage, VH, and a correspondent lower voltage, VL, respectively. Logical data may be represented in other alternative ways. For example logical data 1 could be represented by a signal bounce from VL to VH. The entire duration of the logical data 1 is T1; the voltage is raised from VL to VH after duration T2 from the beginning; and then the voltage is further returned to VL after duration T3.
Signals, which are produced by a typical clock generator (TG), have fixed periods. A main clock (MC) with a period T1 is designated as the basis of the logical data 1. A first clock (C1) has the same period of MC is delayed for a duration of T2. Similarly, a second clock (C2) also has the same period as MC is delayed fro a duration of T2+T3. Both of C1 and C2 are produced by applying different delay lines on signals of MC. In order to generate a pulse such as logical data 1, it is required to combine a pattern signal (P), MC, C1, and C2. The pattern signal (P) is used to provide a combination of VH and VL.
In the consequence, as shown in FIG. 1B, a typical driver comprises a clock generator (TG), a pattern generator (PG), a programmable data selector (PDS), a format controller (FC), and a voltage input (VI). Timing clock sequences such as above-mentioned MC, C1, and C2 are generated by the clock generator. Varied patterns could be generated by the pattern generator and be further directed to designated paths by the programmable data selector. At last, pulses are modulated by the format controller and are amplified in an appropriate range of voltage by the voltage input.
To summarize, the generation of test pulses is to combine the timing clock sequences from the TG with the patterns from the PG by the format controller. And the delay lines are also required to produce varied timing clock sequences. Moreover, the working clock of the electronic element goes higher, and the delayed duration of delay line goes shorter in contrary. However, for the test on high frequency electronic elements such as radio frequency (RF) communication chips, the delay duration of digital delay line may not be short enough to fulfill the requirement of test. Instead, it requires analog delay lines to produce qualified short delay duration. Most drivers are made of ASIC that could provide merely some certain fixed timing clock sequences. Because different test electronic elements are generated from different patterns, these patterns should be generated from varied timing clock sequences that ASIC drivers could not provide. For current test apparatus on high frequency electronic elements, the shortcomings include high costs, lack of reusability, and the need of excess analog logics. It is desired to have a new method and system for solving these mentioned shortcomings to reduce costs and increase test performance.